To the best of Applicants' knowledge, there are two relevant prior art schemes which deal with correcting erroneous instructions. One prior art system is an error detection and correction arrangement. This involves an error correction system which introduces a number of parity bits in the word to be executed. When a parity error has been determined, the error correction circuitry determines the location of the error (usually a bit which has failed) and corrects the error. Under this approach, the intended operation of the data processing system must be delayed until the error correction logic has completed its operations. Since most of the time there is no error detected, the overall processing throughout is deleteriously affected. In addition, the parity circuitry required for this operation is complex since a number of additional bits are required in order to determine exactly where the error has occurred. More importantly, the error correction scheme does nothing to determine whether the basic data was itself bad; it merely determines whether an error has occurred in the reading of data. If the data was bad to begin with, the error correction system does nothing to indicate this problem.
The second prior art system involves the storing of a bad instruction upon its being detected, with the data processing system remembering (i.e., storing) the operations which occurred after the bad instruction, up to the time it was detected as bad. Upon determining the error, the data processing system uses the stored information about the intervening operations to "reset" its condition, so that the operations associated with the error are negated. The problem with this approach is that the circuitry required is quite detailed and complex and adds significantly to the overall cost of the machine. More importantly, the execution of a bad instruction can have some subtle side effects which even the most detailed logic and "resetting" will not be able to cure.
The present invention greatly improves over both of the above schemes while introducing only a few additional elements. Further, the present invention works from an initial premise or assumption that the incorrect instruction was caused by a transient or temporary hardware fault rather than a permanent or "hard" hardware breakdown. If, however, a second error occurs consecutively for the same location, then the presumption shifts and it is presumed that there is a "hard" hardware failure requiring remedial action. The present invention also provides for signalling the occurrence of such second errors so that such remedial action can be taken.